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pdiag pad enable = 0; default on power-up allowing external control of the pdiag in bit 3
5 dasp out This bit is the device active slave present signal output. This pin is open-collector with an
external pull-up resistor. The DASP bit must be set to logic 1 in order to determine if any
other device is driving this signal.
dasp out = 1; writing logic 1 to this bit drives DASP HIGH if the pad enable ( dasp enable
bit 4) is set to logic 1. It is recommended that this bit is written LOW and that the enable
bit is driven to emulate an open-collector output.
dasp out = 0; writing logic 0 to this bit sets the DASP pin LOW if the pad enable (dasp
enable bit 4) is set to logic 1
4 dasp pad this bit default is an input to the SAA7391
enable
dasp pad enable = 1; writing logic 1 to this bit enables the DASP driver output of the
SAA7391
dasp pad enable = 0; default on power-up allowing external control of the dasp in bit 2
3 pdiag in this bit is the passed diagnostics signal input to the SAA7391, only valid if pdiag enable
bit 6 is set to logic 0 (default = 0)
2 dasp in this bit is the device active slave present signal input to the SAA7391, only valid if
dasp enable bit 4 is set to logic 0 (default = 0)
0 hosthipi This bit allows the host interface to increase its priority rating when requesting a data
transfer between itself and the SAA7391 memory processor. With host high priority set the
host data transfer requests are given the second highest priority, the highest given to the
microcontroller.
hosthipi = 1; writing logic 1 increase host interface priority above all other data transfer
requests, bar the microcontroller.
hosthipi = 0; writing logic 0 to this bit (default setting) gives low priority to the host interface
data transfer request.
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Philips Semiconductors Objective specification
ATAPI CD-R block encoder/decoder SAA7391
7.5.4 TRANSFER COUNTER
The transfer counter register defines the total transfer length to be transferred to or from the host. This register is loaded
by the microcontroller and decrements synchronously with the DBCH/DBCL registers. The remainder packet size can be
loaded from the transfer counter into DBCH or DBCL when the transfer counter value becomes less than the packet size
store.
Table 82 Transfer counter register
ADDRESS ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FFA0H RW byte count (bits 7 to 0)
FFA1H RW byte count (bits 15 to 8)
FFA2H RW byte count (bits 23 to 16)
FFA3H RW byte count (bits 31 to 24)
7.5.5 PACKET SIZE STORE
The packet size store will be loaded from the DBCH or DBCL registers when the host writes to ACMD, provided the drive
is selected. It may also be updated by the microcontroller. The DBCH/DBCL registers will be auto loaded from the packet
size store on condition that the transfer counter contains an equal or greater value than that held in the packet size store.
Table 83 Packet size store
ADDRESS ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FFA4H RW byte count (bits 7 to 0)
FFA5H RW byte count (bits 15 to 8)
7.5.6 SEQUENCER STATUS
7.5.6.1 Sequencer status
For debugging the auto sequencer a sequencer status register has been provided (address FF6AH). A suspend
sequence bit has been provided ( hiseq bit 4; see Table 76), which if asserted (logic 1) will suspend the auto sequencer
operation at its present state. The suspended state may then be read from the sequencer state register. If the sequencer
state is a write to a host interface registers state, then the sequencer will perform the write operation after the suspend
sequencer bit is negated by the microcontroller.
Table 84 Sequencer status: address FFA6H (note 1)
ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
R - - sequencer state (bits 5 to 0)
Note
1. For an explanation of the sequence state number see the user guide. The user guide is available from product
support.
1997 Aug 01 49
Philips Semiconductors Objective specification
ATAPI CD-R block encoder/decoder SAA7391
An interrupt is associated with HOSTBYTECOUNT
7.5.6.2 Auxiliary block memory processor registers
becoming zero. This is an indication to the microcontroller
The registers given in Table 85 are located in the Aux
to reload the HOSTCURSEG and HOSTBYTECOUNT
block of the and control the SAA7391 memory processor
registers for the next transfer.
buffer management. Transfer to/from the host is possible
The HOSTCURSEG, HOSTBYTEOFFSET and
as soon as the HOSTBYTECOUNT is non-zero, and the
HOSTBYTECOUNT registers indicate the address of the
HOSTCURSEGCNT is non-zero.
next byte to be transferred to or from the host, in order that
The chan0 and chan1 bits control the sequencing of
the status of the interface may be read. The operation of
sub-block transfers. They indicate the number of
the HOSTBYTECOUNT and HOSTBYTEOFFSET
offset/length pairs to use for each block being transferred.
registers is given in Table 85.
Normally only channels 0 and 1 are needed for Mode 2
host transfers. Channels 2 and 3 are available for special
READ-CD command options.
Table 85 Host interface DMA pointers
ADDR ACCESS NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FF45H RW HOSTCURSEG-L s7 s6 s5 s4 s3 s2 s1 s0
FF44H RW HOSTCURSEG-H chan1 chan0 - s12 s11 s10 s9 s8
FF66H RW HOSTCURSEGCNT b7 b6 b5 b4 b3 b2 b1 b0
FF59H RW HOSTSUBBLKOFFSET0-L a7 a6 a5 a4 a3 a2 a1 a0
FF58H RW HOSTSUBBLKOFFSET0-H autoform form - - a11 a10 a9 a8
FF5DH RW HOSTSUBBLKOFFSET1-L a7 a6 a5 a4 a3 a2 a1 a0
FF5CH RW HOSTSUBBLKOFFSET1-H autoform form - - a11 a10 a9 a8
FF51H RW HOSTSUBBLKOFFSET2-L a7 a6 a5 a4 a3 a2 a1 a0
FF50H RW HOSTSUBBLKOFFSET2-H autoform form - - a11 a10 a9 a8
FF55H RW HOSTNEXTSEG-L a7 a6 a5 a4 a3 a2 a1 a0
FF54H RW HOSTNEXTSEG-H autoform form - a12 a11 a10 a9 a8
FF5BH RW HOSTSUBBLKCOUNT0-L c7 c6 c5 c4 c3 c2 c1 c0
FF5AH RW HOSTSUBBLKCOUNT0-H - - - - c11 c10 c9 c8
FF5FH RW HOSTSUBBLKCOUNT1-L c7 c6 c5 c4 c3 c2 c1 c0
FF5EH RW HOSTSUBBLKCOUNT1-H - - - - c11 c10 c9 c8
FF53H RW HOSTSUBBLKCOUNT2-L c7 c6 c5 c4 c3 c2 c1 c0
FF52H RW HOSTSUBBLKCOUNT2-H - - - - c11 c10 c9 c8
FF57H RW HOSTNEXTSEGCOUNT c7 c6 c5 c4 c3 c2 c1 c0
FF56H RW HOSTRELOADFLAGS rel1 rel2 - - c11 c10 c9 c8
FF43H RW HOSTBYTEOFFSET-L a7 a6 a5 a4 a3 a2 a1 a0
FF42H RW HOSTBYTEOFFSET-H autoform form - - a11 a10 a9 a8
FF65H RW HOSTBYTECOUNT-L c7 c6 c5 c4 c3 c2 c1 c0
FF64H RW HOSTBYTECOUNT-H - - - - c11 c10 c9 c8
FF69H RW HOSTRELSEG-L s7 s6 s5 s4 s3 s2 s1 s0
FF68H RW HOSTRELSEG-H chan1 chan0 - s12 s11 s10 s9 s8
FF6BH RW AUX_FORM_SCAN c7 c6 c5 c4 c3 c2 c1 c0
1997 Aug 01 50
Philips Semiconductors Objective specification
ATAPI CD-R block encoder/decoder SAA7391
Table 86 Decoding chan bits
VALUE DESCRIPTION
00 use extent 0
01 use extent 0 to 1
10 use extent 0 to 2
11 use extent 0 to 3 (see also Section 7.5.8)
7.5.7 HOST INTERFACE DMA SPECIAL BITS
Table 87 Decoding bits 7 and 6 of HOSTSUBBLKOFFSETX-H (note 1)
BIT NAME VALUE DESCRIPTION
7 autoform 0 unconditional transfer
1 only transfer if previous Form bit matches bit 6
6 form 0 match last Form bit = 0, perform this transfer if success else reload host registers
1 match last Form bit = 1, perform this transfer if success else reload host registers
Note
1. The last Form bit is the LSB of the byte that is situated at offset 12 in the current segment pointed at by
HOSTCURSEG. This is the stored Form byte in the header.
7.5.8 AUTOMATIC BLOCK POINTER RELOAD 7.5.9 DMA TRANSFER PROGRAMMING OF THE HOST
PROGRAMMING INTERFACE
If either bit 6 or bit 7 are set in the HOSTRELOADFLAGS The host interface is optimized for the normal read
register, then when the HOSTRELOADCOUNT register commands, handling all data transfers or contiguous data
becomes zero, the value of HOSTCURSEGCNT will be plus header requests automatically, with auto Form
copied from HOSTNEXTSEGCOUNT and detection in Mode 2.
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